作者：胡詣哲

作者簡介：胡詣哲博士，EETOP論壇資深版主，現為中國科學技術大學特任教授，博導，國家優青（海外）入選人。

本論文分享論壇資深版主JoyShockley（胡詣哲博士）及課題組的JSSC最新論文第一篇——電荷域小數分頻全數字鎖相環。

歡迎大家前往論壇支持版主、參與討論及獲取論文下載鏈接。

https://bbs.eetop.cn/thread-988756-1-1.html

這是課題組成立兩年以來第一篇JSSC – 電荷域小數分頻全數字鎖相環。
也是個人第一篇Last Author 文章，希望讀者喜歡。

https://ieeexplore.ieee.org/abstract/document/10981601 （開放獲取，免費下載）

附部分網友留言：

祝賀胡老師，很棒的無私分享，指標也相當優秀

有一個疑問，各種亞采樣等結構抖動指標非常好10~100fs級別，但不知為何業界的PLL似乎更多的選擇傳統CP架構？

Good reference data for ADPLL designers to study that ~~
Thanks~~~

祝賀祝賀，期待ADPLL能有更多應用。

論文部分截圖：

Abstract:

We propose a charge-domain fractional-N all-digital phase-locked loop (ADPLL) that employs charge-steering sampling (CSS) of a sinusoidal reference waveform.

The well-known issue of ΔΣ quantization error in fractional-N operation is compensated by a capacitive digital-to-analog converter (CDAC), which serves the conventional role of a digital-to-time converter (DTC).

This CDAC is further merged with the inherent CDAC of a successive approximation register (SAR) analog-to-digital converter (ADC), which is exclusively used for digitizing the time-error mainly induced by the phase noise (PN).

Initially, the combined CDACs are preset to VDD, and then discharged during a short digitally controlled oscillator (DCO)-divider-triggered pulse via a pseudo-differential MOS pair directly driven by the input reference sinusoidal waveform. Owing to the gentle slope of the reference waveform, the charge-domain fractional-N operation achieves a wide and linear time-error detection (TD) range.

Furthermore, by reinterpreting the SAR ADC output using multi-bit midrise encoding, the effective time-to-digital conversion (TDC) gain is boosted by bang–bang (BB) effects while maintaining fast and robust locking. To accurately model the CSS current, we introduce a damped-sine waveform model incorporating harmonics, providing comprehensive insight into the CSS-TD gain, even with short-channel devices.

Fabricated in 22 nm CMOS, the prototype achieves an rms jitter of 96 fs at 24 GHz with a reference spur of -60 dBc in integer-N mode, while 167.8 fs at approximately 24.5 GHz with a worst in-band spur of -47.8 dBc in fractional-N mode. The occupied area is only 0.08 mm2.

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https://bbs.eetop.cn/thread-988756-1-1.html

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